Synthesis and Implementation of Carry Select Adder Using Binary to Excess-1 Converter and Memo Table

Abstract

As the digital electronics system is getting better with advancement in technology day by day; there is a need to build faster and more efficient devices. Adders are the fundamental building blocks in digital integrated circuit based designs. It plays a vital role in multiplication and other advanced processors design. The binary addition has a vast usage in digital circuits as it is the basic arithmetic operation and which became indispensible in most of the digital systems such as counting ALU, microprocessors and DSP processorsThe main objective of this thesis is to provide high speed and low area in carry select adder by using reusing computation with binary to excess-1 convertor. Up to now most of the researchers have done various techniques at different levels of the design process which have been implemented to reduce the power dissipation of the circuits. To improve the performance of this multiplier, CSLA is replaced by binary excess 1 counter which not only reduces the area at gate level but also reduces power consumption and RCA computation is replaced with memo table. The proposed architecture of carry select adder with excess-1 convertor and memo table is simulated and synthesized in XilinxISE14.5.