Design of Energy Recovery Flip Flop Using Soft Error Robust Algorithm for Low Power Resonant Clocking Applications

Abstract

The development of a high-performance processor has become a major concern as the semiconductor industry has advanced. One of the most important aspects of almost any optical signal processing program is flip flop. The Soft Error Robust Algorithm is used to model the low-power Energy Recovery Flip Flop in this project. To achieve low power dissipation, the SCCER Flip Flop's basic building block is constructed using the SVL algorithm. The Energy Recovery Flip Flop saves a lot of power while the Flip Flops are idle, and there's no visible overhead compared to the original flip flop. Compared to D-Flip Flop using SVL algorithm, SCCER Flip Flop saves 34.2% of power using SVL algorithm. Thus the simulation results have shown that the proposed Energy Recovery Flip Flop using Soft Error Robust offers low power consumption and can be well suited for Low Power Resonant Clocking applications. Simulation is performed using the Tanner EDA tool in 180nm technology and the results indicate a major improvement in Low power consumption.