Development of 15 Level Cascaded H-H-T Multilevel Inverter

Authors

  • R. Ramaprabha  Associate Professor, Department of Electrical and Electronics Engineering Sri Sivasubramaniya Nadar College of Engineering, Chennai, Tamil Nadu, India
  • V. Aadhavan  UG Students, Department of Electrical and Electronics Engineering Sri Sivasubramaniya Nadar College of Engineering, Chennai, Tamil Nadu, India
  • K. Arun  UG Students, Department of Electrical and Electronics Engineering Sri Sivasubramaniya Nadar College of Engineering, Chennai, Tamil Nadu, India
  • V. Arun  

Keywords:

MLI, H-H-T, levels, Mat Lab.

Abstract

In recent years, multilevel inverters have emerged as a very important alternative in the area of high power medium voltage energy control. Multilevel inverters (MLI) have been receiving increased attention for their capability of high voltage operation, low electromagnetic interference (EMI) and higher efficiency. The inverter plays a vital role in any renewable based power generation system, as the power extracted from the renewable source is dc. MLI uses power semiconductor devices and dc sources (batteries/capacitors) to synthesis staircase output voltage waveform. By increasing number of levels improving its spectral quality. Numerous topologies and modulation strategies have been introduced and studied extensively in recent literature for utility and drive applications. Although there are a large number of multilevel inverter topologies in the literature, in this work, the most common cascaded topology with H-H-T structure is implemented and tested.

References

  1. S. Kouro, J. Rodriguez, B. Wu, S. Bernet and M. Perez (2012). “Powering the future of industry: High-power adjustable speed drive topologies”. IEEE Ind. Appl. Mag., vol. 18, no. 4, pp. 26-39.
  2. J. Rodriguez, J.-S. Lai and F. Z. Peng (2002). “Multilevel inverters: A survey of topologies controls and applications”. IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738.
  3. K. Dhineshkumar, C. Subramani, A. Geetha and C. Vimala (2019), “Performance analysis of PV powered multilevel inverter”. International Journal of Electrical and Computer Engineering, vol.9, no.2, pp. 753-760.
  4. I. Sarkar and B. G. Fernandes (2017). “A nine-level hybrid symmetric cascaded multilevel converter for induction motor drive”. Sadhana 42, pp. 1389–1400.
  5. Jagdish Kumar and Jaimala Gambhir (2015), Different multilevel inverter topologies with reduced number of devices. Conference: 2015 2nd International conference on recent advances in engineering & computational sciences (RAECS). DOI: 10.1109/RAECS.2015.7453375.
  6. S. Divya and R. Rebiya (2013). “Modified multilevel inverter topology for driving a single phase induction motor”. Vol. 2, no.1, pp. 288-296.
  7. M. Kavitha, A. Arunkumar, N. Gokulnath and S. Arun (2012). “New cascaded h-bridge multilevel inverter topology with reduced number of switches and sources”. Journal of Electrical and Electronics Engineering, vol. 2, no. 6, pp. 26-36.
  8. V. Jammala, S. Yellasiri and A. K. Panda (2018). “Development of a new hybrid multilevel inverter using modified carrier SPWM switching strategy”. IEEE Trans. Power Electron. , vol. 33, pp. 8192– 8197.
  9. H. Yu, B. Chen, W. Yao and Z. Lu (2018). “Hybrid seven-level converter based on T-Type converter and H-bridge cascaded under SPWM and SVM”. IEEE Trans. Power Electron. Vol. 33, pp. 689– 702.
  10. H. Akagi (2017). “Multilevel converters: Fundamental circuits and systems”. Proc. IEEE 2017, 105, pp. 2048–2065.
  11. S. H. Kang and F. S. Lee (2008). “A new structure of H-bridge multilevel inverter”. In Proceedings of the Annual Fall Conference of Power Electronics (KIPE Conference), Goyang, Korea, 31 October 2008; pp. 388–390.
  12. J. Ebrahimi, E. Babaei and G. B. Gharehpetian (2012). “A new multilevel converter topology with reduced number of power electronic components”. IEEE Trans. Ind. Electron., vol. 59, pp. 655– 667.
  13. E. Samadaei, S. A. Gholamian, A. Sheikholeslami and J. Adabi (2016). “ An envelope type (E-Type) module: Asymmetric multilevel inverters with reduced components”. IEEE Trans. Ind. Electron., vol. 63, pp. 7148–7156.
  14. E. Samadaei, A. Sheikholeslami, S. A. Gholamian and J. Adabi (2017). “A square T-type (ST-Type) module for asymmetrical multilevel inverters”. IEEE Trans. Power Electron., vol. 99, pp. 987– 996.
  15. M. Jayabalan, B. Jeevarathinam, and T. Sandirasegarane (2017). “Reduced switch count pulse width modulated multilevel inverter”. IET Power Electron., vol.10, pp.10–17.
  16. S. P. Gautam, S. Gupta and L. K. Sahu (2016). “Reduction in number of devices for symmetrical and asymmetrical multilevel inverters”. IET Power Electron., vol. 9, pp. 698–709.
  17. www.mathworks.com.

International Journal of Scientific Research in Science and Technology

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Published

2021-04-10

Issue

Volume 9, Issue 1, March-April-2021

Section

Research Articles

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How to Cite

[1]
R. Ramaprabha, V. Aadhavan, K. Arun, V. Arun, " Development of 15 Level Cascaded H-H-T Multilevel Inverter, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 9, Issue 1, pp.340-345, March-April-2021.