Scaling Theory Model for Ferroelectric Surrounding Gate TFET Using Negative Capacitance

Authors

  • Dr. R. Manjith  Associate Professor, Department of Electronics and communication Engineering, Dr. Sivanthi Aditanar College of Engineering, Tamil Nadu, India
  • J. Agnes Sorna Niruba  ME VLSI Student, Department of Electronics and communication Engineering, Dr. Sivanthi Aditanar College of Engineering, Tamil Nadu, India

Keywords:

Tunnel field effect transistor (TFET), Stacked Gate, Analytical Modelling, Poisson equation, Surface potential, Electric field.

Abstract

In this paper, an analytical model for modified Ferroelectric Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Furthermore, taking advantage of Gate stack engineering's scaling advantages and dual material engineering's high degree performance, the two have been combined in a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO2/high-k and dual material (DM). By solving 2D Poisson's equation with matching device boundary conditions, the two-dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are constructed. A mathematical expression for the band-to-band (BTB) Tunnelling generation rate is obtained using Kane's formula, and then used to compute the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. The mathematical results have been verified using the simulated results obtained from ANSYS, a 3-D device simulator. In addition, the modelled TFET is implemented by using inverter circuit.

References

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International Journal of Scientific Research in Science and Technology

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Published

2021-04-10

Issue

Volume 9, Issue 1, March-April-2021

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Dr. R. Manjith, J. Agnes Sorna Niruba, " Scaling Theory Model for Ferroelectric Surrounding Gate TFET Using Negative Capacitance, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 9, Issue 1, pp.557-564, March-April-2021.