HUB Floating-Point Adder Using Double Path

Authors

  • Dr. S. Ramesh  Professor Department of ECE, KPR Institute of Technology Coimbatore, Tamil Nadu, India
  • Saravanavel K  Student (ME – VLSI) KPR Institute of Technology, Coimbatore, Tamil Nadu, India

Keywords:

Component, Formatting, Style, Styling, Insert

Abstract

Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point adder for FPGA which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA

References

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International Journal of Scientific Research in Science and Technology

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Published

2021-04-10

Issue

Volume 9, Issue 1, March-April-2021

Section

Research Articles

License

Copyright (c) IJSRST

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Dr. S. Ramesh, Saravanavel K, " HUB Floating-Point Adder Using Double Path, International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011, Volume 9, Issue 1, pp.708-717, March-April-2021.