Power Efficient and Modified Transmission Technology Based Sram Cell for Core Memories

Authors

  • Perumalla Suresh  M.Tech Scholar, Department of ECE, Shree Rama Educational Society group of Institutions, Tirupati, India.
  • P Giri Babu  Associate Professor, Department of ECE, Shree Rama Educational Society group of Institutions, Tirupati, India.

Keywords:

SRAM, IOT applications, Low power, power gating.

Abstract

The suggested circuit in this project is designed for IoT applications employing a modified transmission gate based SRAM cell that eliminates the need for peripheral circuitry during read operations. Biomedical systems that operate in the sub-threshold region with near-perfect efficiency require several kB of embedded memory. SRAMs account for 70% of the die area, which means they consume the most power and consume the most silicon. In the read operation, this topology provides a smaller area, less delay, lower power consumption, and better data stability. The SRAM cell is made of 45nm CMOS and runs at 0.45 V.

References

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International Journal of Scientific Research in Science and Technology

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Published

2022-09-30

Issue

Volume 9, Issue 5, September-October-2022

Section

Research Articles

License

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Perumalla Suresh, P Giri Babu "Power Efficient and Modified Transmission Technology Based Sram Cell for Core Memories" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 9, Issue 5, pp.08-15, September-October-2022.