A Novel Three Stage Comparator Using Lector Approach
Keywords:
Three stage comparator, Lector Approach.Abstract
This brief presents a three-stage comparator and its modified version to reduce power consumption by using Lector approach. Compared to the traditional three-stage comparator, this novel design of comparator in this work reduces the power consumption. In Lector approach, we are inserting additional transistors in such a way that gate terminals of these extra transistors should have connected with complementary side of output node as per the logic. By this connection, some extra resistance will be added between the paths from supply to ground, which leads to reduction in leakage current. This greatly reduces the leakage power consumption. This proposed design is simulated using Tanner EDA employing 45nm CMOS Technology.
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