Object Detection Using Adaptive Block Partition and RCNN Algorithm

Authors

  • R. Ajay Krishnaraju  Department of ECE, Rajiv College of Engineering and Technology,Puducherry,India
  • J. Poovarasan  Professor, Department of ECE, Rajiv College of Engineering and Technology,Puducherry,India
  • S. Santhies Kumar  
  • S. Surya  
  • P. Tamilselvan  

DOI:

https://doi.org/10.32628/IJSRST523103196

Keywords:

IMM, System on-Chip, High-Level Synthesis

Abstract

Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, cryptography, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. To overcome this issue, a hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq®-7000 System on-Chip (SoC) device consists of Dual-core Cortex™-A9 processors which provides computing ability to perform with the help of software libraries using Vivado® High-Level Synthesis (HLS). The acceleration of object detection algorithms include Sobel-Feldman filter, posterize and threshold filter algorithms implemented with 1920 x 1080 image resolutions for real-time object detection. The implementation results exhibit effective resource utilization such as 45.6% of logic cells, 51% of Look-up tables (LUTs), 29.47% of Flipflops, 15% of Block RAMs and 23.63% of DSP slices under 100 MHz frequency on comparing with previous works. There are a few reasons why tracking is preferable over detecting objects in each frame. Tracking facilitates in identifying the identity of various items across frames when there are several objects. Object detection may fail in some instances, but tracking may still be achievable which takes into account the location and appearance of the object in the previous frame. The key hurdles in real-time image and video processing applications are object tracking and motion detection. Some tracking algorithms are extremely fast because they perform a local search rather than a global search. Tracking algorithms such as meanshift, Regional Neural Network probabilistic data association, particle filter, nearest neighbor, Kalman filter and interactive multiple model (IMM) are available to estimate and predict the state of a system.

References

  1. S.A. Fahmy, K. Vipin, FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications. Comput. Surveys 51, pp. 1-39, 2018.
  2. Xilinx, ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoC: User Guide (2017).[Online].https://www.xilinx.com/support/documentation/boards_and_kits/ zc702_zvik/ug850-zc702-eval-bd.pdf. (Accessed on 23rd March, 2022)
  3. Xilinx Inc.: Zynq-7000 all programmable SoC technical reference manual. (2021). (Accessed on 23rd March, 2022) Available at: https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000- TRM.pdf
  4. Xilinx Inc, “Vivado Design Suite tutorial high level synthesis, UG871 (v 2014.1) May 6, 2014,” UG871 (v 2014.1) May 6, 2014. [Online]. Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug871- vivado-high-level-synthesis-tutorial.pdf. (Accessed on 23rd March, 2022)
  5. P. Babu, E. Parthasarathy, “Reconfigurable FPGA Architectures: A Survey and Applications,” J. Inst. Eng. India Ser. B 102, pp. 143–156, 2021.
  6. J. C. Mora, E. C. Gallego and S. S. Solano, “Hardware/software co-design of video processing applications on a reconfigurable platform,” in Int. Conf. on Industrial Technology (ICIT), Seville, Spain: IEEE, pp. 1694–1699, 2015.
  7. K. F. Kong Wong, V. Yap and T. P. Chiong, “Hardware accelerator implementation on FPGA for video processing,” in IEEE Conf. on Open Systems (ICOS), Kuching, Malaysia, pp. 47–51, 2013.
  8. A. L. Sangiovanni-Vincentelli et al. “Defining Platform-Based Design,” In EEDesign. Available at www.eedesign.com/story/OEG20020204S0062). (Accessed on 23rd March, 2022) 84
  9. L. Kechiche, L. Touil and B. Ouni, “Real-time image and video processing: Method and architecture,” in 2nd Int. Conf. on Advanced Technologies for Signal and Image Processing (ATSIP), IEEE, Monastir, Tunisia, pp. 194–199, 2016.
  10. J. G. Pandey, A. Karmakar and S. Gurunarayanan, “Architectures and algorithms for image and video processing using FPGA-based platform,” in 18th Int. Sym. on VLSI Design and Test (VDAT), IEEE, pp. 1, 2014.
  11. J. Rettkowski, A. Boutros and D. Göhringer, “HW/SW co-design of the HOG algorithm on a Xilinx Zynq SoC,” Journal of Parallel and Distributed Computing, vol. 109, pp. 50–62, 2017.
  12. S. Madhava Prabhu and S. Verma, "A Comprehensive Survey on Implementation of Image Processing Algorithms using FPGA," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 2020, pp. 1-6, doi: 10.1109/ICRAIE51050.2020.9358384.
  13. Ali Azarian, Mahmood Ahmadi, “Reconfigurable Computing Architecture: Survey and introduction,” in 2nd International Conference on Computer Science and Information Technology, IEEE, Beijing, China, pp. 269–27, 2009.
  14. A. DeHon, "Reconfigurable Architectures for General-Purpose Computing", Technical Report Massachusetts Institute of Technology, 1996.
  15. I. Kuon, R. Tessier and J. Rose, "FPGA Architecture: Survey and Challenges", J. Found. and Trends in Electronic Design Automation, vol. 2, no. 2, pp. 135-253, 2008.
  16. K. Compton and S. Hauck, "Reconfigurable computing: A survey of systems and software", ACM Computing Surveys, vol. 34, no. 2, pp. 171-211, 2002.
  17. R. Cumplido, M. Gokhale and M. Huebner, “Guest Editorial: Special issue on Reconfigurable Computing and FPGA technology,” Journal of Parallel and Distributed Computing, vol. 133, pp. 359–361, 2019.
  18. C. Claus, W. Stechele and A. Herkersdorf, “Autovision – A run-time reconfigurable MPSoC architecture for future driver assistance systems,” IT- Information Technology, vol. 49, no. 3, pp. 181–187, 2007. 85
  19. C. Khongprasongsiri, P. Kumhom, W. Suwansantisuk, T. Chotikawanid, S. Chumpol et al., “A hardware implementation for real-time lane detection using high-level synthesis,” in International Workshop on Advanced Image Technology (IWAIT), Chiang Mai, Thailand: IEEE, pp. 1–4, 2018.
  20. D. G. Bailey, “Image processing using FPGAs,” Journal of Imaging, vol. 5, no. 53, pp. 1–4, 2019.
  21. M. Kowalczyk, D. Przewlocka and T. Krvjak, “Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC,” in Conf. on Design and Architectures for Signal and Image Processing (DASIP), Porto, Portugal, pp. 37–42, 2018.
  22. A. B. Amara, E. Pissaloux and M. Atri, “Sobel edge detection system design and integration on an FPGA based HD video streaming architecture,” in 11th Int. Design & Test Sym. (IDT), Hammamet, Tunisia, pp. 160–164, 2016.
  23. E. Onat, “FPGA implementation of real time video signal processing using Sobel, Robert, Prewitt and Laplacian filters,” in 25th Signal Processing and Communications Applications Conf. (SIU), Antalya, Turkey, pp. 1–4, 2017.
  24. R. Tessier, I. Kuon, J. Rose, “FPGA architecture: survey and challenges,” Found. Trends Electron. Des. Autom. 2(2), pp. 135–253, 2008.
  25. Y. Fang, L. Yu and S. Fei, "An Improved Moving Tracking Algorithm With Multiple Information Fusion Based on 3D Sensors," in IEEE Access, vol. 8, pp. 142295-142302, 2020, doi: 10.1109/ACCESS.2020.3008435.

International Journal of Scientific Research in Science and Technology

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Published

2023-06-30

Issue

Volume 10, Issue 3, May-June-2023

Section

Research Articles

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How to Cite

[1]
R. Ajay Krishnaraju, J. Poovarasan, S. Santhies Kumar, S. Surya, P. Tamilselvan "Object Detection Using Adaptive Block Partition and RCNN Algorithm" International Journal of Scientific Research in Science and Technology(IJSRST), Online ISSN : 2395-602X, Print ISSN : 2395-6011,Volume 10, Issue 3, pp.1009-1023, May-June-2023. Available at doi : https://doi.org/10.32628/IJSRST523103196