Area Efficient Approximate Multiplier Using 4 : 2 Compressors with Improved Accuracy

Abstract

Fast implementations based on approximation technology have revolutionized the field of circuit design, enabling the development of high-performance and fault-tolerant circuits. However, this increased performance often comes at the cost of reduced accuracy, which may not be critical for many applications. They are notably required in a variety of settings since these methods also attempt to reduce system complexity, latency, and power consumption.In order to reduce size, latency, and power consumption while retaining a same level of accuracy, the aim of this project is to create and test an approximation compressor. In comparison to a precise 4:2 compressor, the suggested 4:2 compressor approximation has a noticeably smaller footprint, less power loss, and lower latency. Dadda multipliers in 8-bit and 16-bit can be easily produced with these upgraded compressors.These Dadda multipliers, constructed with the improved compressors, offer a similar level of precision as modern approximation multipliers. With no reduction in computation accuracy, this results in an improvement in total performance.