An Efficient Method Using Modified Transmission Gate for Bio Medical Applications

Authors

  • Dr. Abraham Mathew Associate Professor, Department of Electronics and Communication Engineering, N.B.K.R Institute of Science and Technology, Vidyanagar, Tirupati(D), Andhra Pradesh, India Author
  • B. Manasa UG Students, Department of Electronics and Communication Engineering, N.B.K.R Institute of Science and Technology, Vidyanagar, Tirupati(D), Andhra Pradesh, India Author
  • D. Keerthi UG Students, Department of Electronics and Communication Engineering, N.B.K.R Institute of Science and Technology, Vidyanagar, Tirupati(D), Andhra Pradesh, India Author
  • V. Madhumitha UG Students, Department of Electronics and Communication Engineering, N.B.K.R Institute of Science and Technology, Vidyanagar, Tirupati(D), Andhra Pradesh, India Author
  • K. Harsha Vardhan UG Students, Department of Electronics and Communication Engineering, N.B.K.R Institute of Science and Technology, Vidyanagar, Tirupati(D), Andhra Pradesh, India Author

Keywords:

SRAM, IoT, Low Power, Sub-threshold Operation

Abstract

A novel method is presented here, using modified transmission gate exclusively for IOT application in biomedical area. The major advantage is there is no peripheral circuitry requirement during a read operation. For the purpose of efficient power consumption SRAMs are used in our project. We focus on biomedical area as it typically operates in the sub-threshold domain with good efficiency. In order to reduce the power consumption for the circuit we are applying the power gating technique at the supply node. The proposed design is used for low power technology as well as a technology for low power consumption. Thus, by using the power gating technique we are making the 8T SRAM as power efficient and effective read operation stability.

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References

N. Maroof and B.-S. Kong, “10T SRAM using Half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 4, pp. 1193–1203, Apr. 2017.

T.-H. Kim, J. Liu, and C. H. Kim, “A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785–1795, Jun. 2009.

N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.

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Published

25-04-2025

Issue

Section

Research Articles