Implementation of Logic-Locking Technique Based on Probability Using Back End Tool

Authors

  • P. Rajesh Assistant Professor, Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Sompalli Charan Sai Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Vellala Sai Sri Pranathi Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Udatha Kavya Sree Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Thippareddy Asuvardhan Reddy Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • A R Kushal Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author

Keywords:

DSCH And MICROWIND, Probability Based Locking

Abstract

Integrated circuit (IC) piracy and overproduction are serious issues that threaten the security and integrity of a system. Logic locking is a type of hardware technique where additional key gates are inserted into the circuit. Here probability-based logic-locking technique to protect the design of a circuit. Our proposed technique, called “ProbLock”, can be applied to both combinational and sequential circuits through a critical selection process. We have to use filtering process to select the best location of key gates based on various constraints. Each step in the filtering process generates a subset of nodes for each constraint.  The Probability-Based Logic-Locking Technique is a security measure that aims to protect the confidentiality and integrity of integrated circuits. This technique uses a combination of DSCH and MICROWIND tools to generate logic-locked designs that are resistant to reverse engineering attacks. The logic-locking process involves adding additional gates to the design, which are controlled by secret keys, and thereby obfuscating the original circuit's functionality. The probability-based approach introduces randomness in the process, making it difficult for attackers to determine the correct key. By using a stochastic algorithm, the locking mechanism generates a set of gates that have a probability distribution based on the secret key. The resulting design is then verified for correctness and functionality using MICROWIND tools.  This abstract presents a novel technique for generating logic-locked designs using DSCH and MICROWIND tools with a probability-based approach. The technique aims to provide increased security for integrated circuits, making them less vulnerable to reverse engineering attacks. The proposed technique is evaluated using simulations and experimental results, which demonstrate the effectiveness of the approach in preventing unauthorized access to sensitive information stored in the circuit.              

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References

Mellor, J.; Shelton, A.; Yue, M.; Tehranipoor, F. Attacks on logic locking obfuscation techniques. In Proceedings of the 2021 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 10–12 January 2021; pp. 142–149.

Forte, D.; Bhunia, S. Hardware Protection through Obfuscation; Tehranipoor, M., Ed.; Springer International Publishing: Berlin/Heidelberg, Germany, 2017; pp. 1–349.

Lee, Y.; Touba, N.A. Improving logic obfuscation via logic cone analysis. In Proceedings of the 2015 16th Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico, 25–27 March 2015; pp. 1–6.

Yasin, M.; Rajendran, J.J.V.; Sinanoglu, O.; Karri, R. On Improving the Security of Logic Locking. IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 2016, 1411–1424. [CrossRef]

Amir, S.; Shakya, B.; Xu, X.; Jin, Y.; Bhunia, S.; Tehranipoor, M.; Forte, D. Development and Evaluation of Hardware Obfuscation Benchmarks. J. Hardw. Syst. Secur. 2018, 142–161. [CrossRef]

Yasin, M.; Mazumdar, B.; Rajendran, J.J.V.; Jin, Y.; Sinanoglu, O. SARLock: SAT attack resistant logic locking. In Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, 3–5 May 2016; pp. 236–241.

Tehranipoor, F.; Karimian, N.; Kermani, M.M.; Mahmoodi, H.; Sinanoglu, O. Deep rnn-oriented paradigm shift through bocanet: Broken obfuscated circuit attack. In Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA, USA, 9–11 May 2019; pp. 335–338. [CrossRef]

Brglez, F.; Fujiwara, H. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan. In Proceedings of the International Symposium on Circuits and Systems, Kyoto, Japan, 5–7 June 1985; pp. 663–698.

Brglez, F.; Bryan, D.; Kozminski, K. Combinational Profiles of Sequential Benchmark Circuits. In Proceedings of the International Symposium on Circuits and Systems, Portland, OR, USA, 8–11 May 1989; pp. 1929–1934.

Yasin, M.; Mazumdar, B.; Rajendran, J.J.V.; Sinanoglu, O. TTLock: Tenacious and traceless logic locking. In Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2017), McLean, VA, USA, 1–5 May 2017; p. 166.

engupta, A.; Nabeel, M.; Yasin, M.; Sinanoglu, O. ATPG-based cost-effective, secure logic locking. In Proceedings of the 2018 IEEE 36th VLSI Test Symposium (VTS), San Francisco, CA, USA, 22–25 April 2018; pp. 1–6.

Yasin, M.; Sengupta, A.; Thari Nabeel, M.; Ashraf, M.; Rajendran, J.J.V.; Sinanoglu, O. Provably-Secure Logic Locking: From Theory To Practice. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, Dallas, TX, USA, 30 October–3 November 2017; pp. 1601–1618.

Yang, F.; Tang, M.; Sinanoglu, O. Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) - 2013 Unlocked. IEEE Trans. Inf. Forensics Secur. 2019, 2778–2786. [CrossRef]

Yasin, M.; Zhao, C.; Rajendran, J.J.V. SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. In Proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, 4–7 November 2019; pp. 1–4.

Saha, A.; Saha, S.; Bhattacharya, B.B.; Chowdhury, S.; Mukhopadhyay, D. Lopher: Sat-hardened logic embedding on block ciphers. In Proceedings of the 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 20–24 July 2020; pp. 1–6.

Abdulrahman, A.; Bhunia, S. Scalable Attack-Resistant Obfuscation of Logic Circuits. arXiv 2020, arXiv:2010.15329.

Biere, A. Splatz, Lingeling, Plingeling, Treengeling, YalSAT Entering the SAT Competition 2016. Available online: fmv.jku.at/ papers/Biere-SAT-Competition-2016-solvers.pdf (accessed on 5 October 2021).

Xie, Y.; Srivastava, A. Anti-SAT: Mitigating SAT Attack on Logic Locking. IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 2015, 38, 199–207. [CrossRef]

Miskov-Zivanov, N.; Marculescu, D. Modeling and Optimization for Soft-Error Reliability of Sequential Circuits. IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 2008, 27, 803–816. [CrossRef]

Waksman, A.; Suozzo, M.; Sethumadhavan, S. FANCI: Identification of Stealthy Malicious Logic Using Boolean Functional Analysis. In Proceedings of the 2013 ACM SIGSAC Conference on Computer & Communications Security, Berlin, Germany, 4–8 November 2013; pp. 697–708.

Design Compiler Graphical. Synopsys. 2018. Available online: https://www.synopsys.com/implementation-and-signoff/rtlsynthesis-test/design-compiler-graphical.html (accessed on 5 October 2021).

Subramanyan, P.; Ray, R.; Malik, S. Evaluating the security of logic encryption algorithms. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST2015), Washington, DC, USA, 5–7 May 2015; pp. 137–143.

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Published

16-03-2024

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Research Articles

How to Cite

Implementation of Logic-Locking Technique Based on Probability Using Back End Tool . (2024). International Journal of Scientific Research in Science and Technology, 11(2), 262-272. https://ijsrst.com/index.php/home/article/view/IJSRST52411241

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