Implementation of Logic-Locking Technique Based on Probability Using Back End Tool

Authors

  • P. Rajesh Assistant Professor, Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Sompalli Charan Sai Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Vellala Sai Sri Pranathi Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Udatha Kavya Sree Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • Thippareddy Asuvardhan Reddy Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author
  • A R Kushal Department of Electronics and Communication Engineering, SV College of Engineering (SVCE), Tirupati, A.P. India Author

Keywords:

DSCH And MICROWIND, Probability Based Locking

Abstract

Integrated circuit (IC) piracy and overproduction are serious issues that threaten the security and integrity of a system. Logic locking is a type of hardware technique where additional key gates are inserted into the circuit. Here probability-based logic-locking technique to protect the design of a circuit. Our proposed technique, called “ProbLock”, can be applied to both combinational and sequential circuits through a critical selection process. We have to use filtering process to select the best location of key gates based on various constraints. Each step in the filtering process generates a subset of nodes for each constraint.  The Probability-Based Logic-Locking Technique is a security measure that aims to protect the confidentiality and integrity of integrated circuits. This technique uses a combination of DSCH and MICROWIND tools to generate logic-locked designs that are resistant to reverse engineering attacks. The logic-locking process involves adding additional gates to the design, which are controlled by secret keys, and thereby obfuscating the original circuit's functionality. The probability-based approach introduces randomness in the process, making it difficult for attackers to determine the correct key. By using a stochastic algorithm, the locking mechanism generates a set of gates that have a probability distribution based on the secret key. The resulting design is then verified for correctness and functionality using MICROWIND tools.  This abstract presents a novel technique for generating logic-locked designs using DSCH and MICROWIND tools with a probability-based approach. The technique aims to provide increased security for integrated circuits, making them less vulnerable to reverse engineering attacks. The proposed technique is evaluated using simulations and experimental results, which demonstrate the effectiveness of the approach in preventing unauthorized access to sensitive information stored in the circuit.              

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Published

16-03-2024

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Research Articles

How to Cite

Implementation of Logic-Locking Technique Based on Probability Using Back End Tool . (2024). International Journal of Scientific Research in Science and Technology, 11(2), 262-272. https://ijsrst.com/index.php/home/article/view/IJSRST52411241

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